The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2024

Filed:

Jul. 31, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Manish Arora, Hsinchu, TW;

Yen-Huei Chen, Hsinchu, TW;

Hung-Jen Liao, Hsinchu, TW;

Nikhil Puri, Hsinchu, TW;

Yu-Hao Hsu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01); G11C 7/12 (2006.01); G11C 11/00 (2006.01); G11C 16/04 (2006.01); H10B 41/20 (2023.01); H10B 41/35 (2023.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G11C 7/12 (2013.01); G11C 11/005 (2013.01); G11C 16/0483 (2013.01); H10B 41/20 (2023.02); H10B 41/35 (2023.02);
Abstract

A memory circuit includes first and second memory segments coupled to first and second write lines, and first and second write line circuits coupled to the first and second write lines and configured to receive first and second data signals. The first and second data signals have complementary low and high logical states during a write operation to the first or second memory segment, and each of the first and second data signals has the low logical state during a masked write operation to the first or second memory segment. The first and second write line circuits output, to the first and second write lines, first and second write line signals responsive to the first and second data signals during the write operation and float the first and second data lines during the masked write operation.


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