The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2024

Filed:

May. 31, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jeffrey Erik Schulz, Milpitas, CA (US);

David W. Mendel, Sunnyvale, CA (US);

Dinesh D. Patil, Sunnyvale, CA (US);

Gary Brian Wallichs, San Jose, CA (US);

Keith Duwel, San Jose, CA (US);

Jakob Raymond Jones, San Jose, CA (US);

Assignee:

ALTERA CORPORATION, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H03K 19/173 (2006.01); H04W 56/00 (2009.01);
U.S. Cl.
CPC ...
G06F 13/4045 (2013.01); G06F 13/385 (2013.01); G06F 13/42 (2013.01); G06F 13/4291 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H03K 19/1736 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/1431 (2013.01); H04W 56/0015 (2013.01);
Abstract

An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.


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