The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2024
Filed:
May. 28, 2020
Intel Corporation, Santa Clara, CA (US);
Ang Li, Coquitlam, CA;
Intel Corporation, Santa Clara, CA (US);
Abstract
Systems and devices can include power management circuitry to manage the entry and exit of active state power management (APSM) link states, such as the transition between an active (L0) state and a low power state (e.g., L1). The power management circuitry can cause a downstream component to initiate an ASPM link state change negotiation based on an ASPM link state change condition being met. An ASPM event analysis logic can identify and track events that occur proximate in time to the ASPM link state change and can correlate the occurrences of the event with ASPM link state changes. An ASPM policy tuning logic can use a correlation between the occurrences of the event and ASPM link state changes to adjust or tune the ASPM link state change condition.