The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Sep. 28, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsung-Chieh Hsiao, Shetou Township, TW;

Yu-Feng Yin, Hsinchu County, TW;

Liang-Wei Wang, Hsinchu, TW;

Dian-Hau Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 50/01 (2023.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01);
U.S. Cl.
CPC ...
H10N 50/01 (2023.02); G11C 11/161 (2013.01); H10B 61/22 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02);
Abstract

In a method of manufacturing a semiconductor device, a cell structure is formed. The cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack disposed on the bottom electrode and a hard mask layer disposed on the MTJ stack. A first insulating cover layer is formed over sidewall of the MTJ stack. A second insulating cover layer is formed over the first insulating cover layer and the hard mask layer. A first interlayer dielectric (ILD) layer is formed. The hard mask layer is exposed by etching the first ILD layer and the second insulating cover layer. A second ILD layer is formed. A contact opening is formed in the second ILD layer by patterning the second ILD layer and removing the hard mask layer. A conductive layer is formed in the contact opening so that the conductive layer contacts the MTJ stack.


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