The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Feb. 28, 2020
Applicant:

Kyocera Corporation, Kyoto, JP;

Inventors:

Katsuaki Masaki, Kyoto, JP;

Kentaro Murakawa, Kyotanabe, JP;

Assignee:

KYOCERA CORPORATION, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 23/00 (2006.01); H01L 33/40 (2010.01);
U.S. Cl.
CPC ...
H01L 33/0093 (2020.05); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 33/007 (2013.01); H01L 33/0075 (2013.01); H01L 33/40 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05171 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05611 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/08123 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80365 (2013.01); H01L 2224/80801 (2013.01); H01L 2933/0016 (2013.01);
Abstract

A method of manufacturing a semiconductor element according to the present disclosure includes an element forming step (S) of forming, on an underlying substrate (), a semiconductor element () connected to the underlying substrate () via a connecting portion () and including an upper surface () inclined with respect to a growth surface of the underlying substrate (), a preparing step (S) of preparing a support substrate () including an opposing surface () facing the underlying substrate (), a bonding step (S) of pressing the upper surface () of the semiconductor element () against the opposing surface () of the support substrate () and heating the upper surface () to bond the upper surface () of the semiconductor element () to the support substrate (), and a peeling step (S) of peeling the semiconductor element () from the underlying substrate ().


Find Patent Forward Citations

Loading…