The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Sep. 13, 2023
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Dethard Peters, Höchstadt, DE;

Sascha Axel Baier, Neubiberg, DE;

Tomas Reiter, Ottobrunn, DE;

Sandeep Walia, Villach, AT;

Frank Wolter, Munich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); G01K 7/16 (2006.01); G01R 31/26 (2020.01); G01R 31/27 (2006.01); G01R 31/28 (2006.01); G01R 31/52 (2020.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7815 (2013.01); G01K 7/16 (2013.01); G01R 31/2628 (2013.01); G01R 31/27 (2013.01); G01R 31/2831 (2013.01); G01R 31/52 (2020.01); H01L 29/1608 (2013.01); H01L 29/7805 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source regions of the current sense transistor. The doped resistor region has an opposite conductivity type as the source regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.


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