The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

May. 06, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Te-An Chen, Hsinchu, TW;

Meng-Han Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/16 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 29/16 (2013.01); H01L 29/4236 (2013.01); H01L 29/66484 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes forming a first CPODE dummy poly gate and a second CPODE dummy poly gate on a semiconductor substrate; removing the first CPODE dummy poly gate and a portion of the semiconductor substrate therebelow to form a first trench extending into the semiconductor substrate; filling the first trench with a first dielectric material to form a first isolation structure to isolate the first and second transistors from each other; removing the second CPODE dummy poly gate and a portion of the semiconductor substrate therebelow to form a second trench extending into the semiconductor substrate; and filling the second trench with a second dielectric material having a dielectric composition different from that of the first dielectric material to form a second isolation structure to isolated the third and fourth transistors from each other.


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