The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Oct. 25, 2021
Applicant:

Changxin Memory Technologies, Inc., Anhui, CN;

Inventor:

Feng Lin, Shanghai, CN;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); H01L 22/32 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/06515 (2013.01); H01L 2924/1436 (2013.01);
Abstract

A transmission circuit includes: an upper-layer clock bonding pad configured to transmit a clock signal; M upper-layer data bonding pads configured to transmit data signals; a lower-layer clock bonding pad electrically connected with the upper-layer clock bonding pad, and an area of the lower-layer clock bonding pad is smaller than that of the upper-layer clock bonding pad; and M lower-layer data bonding pads electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence, and an area of a lower-layer data bonding pad is smaller than that of an upper-layer data bonding pad. The upper-layer clock bonding pad and the upper-layer data bonding pads are located on a first layer, the lower-layer clock bonding pad and the lower-layer data bonding pads are located on a second layer.


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