The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Nov. 17, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Leonard P. Guler, Hillsboro, OR (US);

Charles Henry Wallace, Portland, OR (US);

Paul A. Nyhus, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); G06F 1/16 (2006.01); H01L 23/14 (2006.01); H01L 23/50 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5222 (2013.01); G06F 1/16 (2013.01); H01L 21/76838 (2013.01); H01L 23/142 (2013.01); H01L 23/50 (2013.01); H01L 23/528 (2013.01);
Abstract

Methods for fabricating an IC structure, e.g., for fabricating a metallization stack portion of an IC structure, as well as related semiconductor devices, are disclosed. An example fabrication method includes splitting metal lines that are supposed to be included at a tight pitch in a single metallization layer into two vertically-stacked layers (hence the term 'vertical metal splitting') by using helmets and wrap-around dielectric spacers. Metal lines split into two such layers may be arranged at a looser pitch in each layer, compared to the pitch at which metal lines of the same size would have to be arranged if there were included in a single layer. Increasing the pitch of metal lines may advantageously allow decreasing the parasitic metal-to-metal capacitance associated with the metallization stack.


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