The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Feb. 01, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert S. Chappell, Portland, OR (US);

Jared W. Stark, IV, Portland, OR (US);

Joseph Nuzman, Haifa, IL;

Stephen Robinson, Austin, TX (US);

Jason W. Brandt, Austin, TX (US);

Assignee:

Intel CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 12/0802 (2016.01); G06F 21/55 (2013.01); G06F 21/62 (2013.01);
U.S. Cl.
CPC ...
G06F 21/556 (2013.01); G06F 9/30116 (2013.01); G06F 9/30123 (2013.01); G06F 9/30196 (2013.01); G06F 9/3806 (2013.01); G06F 9/3808 (2013.01); G06F 9/3842 (2013.01); G06F 9/3844 (2013.01); G06F 9/4881 (2013.01); G06F 12/0802 (2013.01); G06F 21/62 (2013.01);
Abstract

Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor core includes an instruction fetch circuit to fetch instructions; a branch target buffer comprising a plurality of entries that each include a thread identification (TID) and a privilege level bit; and a branch predictor, coupled to the instruction fetch circuit and the branch target buffer, to predict a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the branch target buffer, and cause the target instruction to be fetched by the instruction fetch circuit.


Find Patent Forward Citations

Loading…