The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Jun. 22, 2023
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jin-Ho Bin, Hanam-si, KR;

Il-Young Kwon, Seoul, KR;

Tae-Hong Gwon, Icheon-si, KR;

Hye-Hyeon Byeon, Pohang-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02);
Abstract

Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.


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