The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Dec. 30, 2021
Applicant:

Unisantis Electronics Singapore Pte. Ltd., Singapore, SG;

Inventors:

Fujio Masuoka, Tokyo, JP;

Nozomu Harada, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 10/00 (2023.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H01L 21/76816 (2013.01); H01L 29/4234 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01);
Abstract

In formation of an SRAM cell, a band-shaped contact hole Cis formed that does not overlap, in plan view. N+ layers, andformed on and at outer peripheries of the top portions of Si pillars, and, that partly overlaps W layersandon P+ layersandconnected to the top portions of Si pillarsand, that is connected in both the X direction and the Y direction, and that extends in the Y direction. A power supply wiring metal layer Vdd that connects the P+ layersandthrough the contact hole Cis formed. After formation of the power supply wiring metal layer Vdd, a word wiring metal layer WL is formed so as to be orthogonal to the power supply wiring metal layer Vdd in plan view.


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