The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Sep. 28, 2021
Applicant:

Stmicroelectronicsa (Rousset) Sas, Rousset, FR;

Inventors:

Abderrezak Marzaki, Aix en Provence, IT;

Romeric Gay, Aix-en-Provence, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H10B 41/35 (2023.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7855 (2013.01); H01L 29/40114 (2019.08); H01L 29/42336 (2013.01); H01L 29/66795 (2013.01); H01L 29/66825 (2013.01); H01L 29/7889 (2013.01); H10B 41/35 (2023.02); H01L 27/0886 (2013.01);
Abstract

A triple-gate MOS transistor is manufactured in a semiconductor substrate including at least one active region laterally surrounded by electrically isolating regions. Trenches are etched on either side of an area of the active region configured to form a channel for the transistor. An electrically isolating layer is deposited on an internal surface of each of the trenches. Each of the trenches is then filled with a semiconductive or electrically conductive material up to an upper surface of the active region so as to form respective vertical gates on opposite sides of the channel. An electrically isolating layer is then deposited on the upper surface of the area of the active region at the channel of the transistor. At least one semiconductive or electrically conductive material then deposited on the electrically isolating layer formed at the upper surface of the active region to form a horizontal gate of the transistor.


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