The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2024
Filed:
May. 23, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/225 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7833 (2013.01); H01L 21/2254 (2013.01); H01L 21/31111 (2013.01); H01L 21/31133 (2013.01); H01L 21/31144 (2013.01); H01L 21/31155 (2013.01); H01L 21/823821 (2013.01); H01L 29/0649 (2013.01); H01L 29/66492 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/7848 (2013.01); H01L 29/785 (2013.01);
Abstract
In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.