The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Aug. 11, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Chih Yuan Chang, New Taipei, TW;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/56 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 24/32 (2013.01); H01L 25/50 (2013.01); H01L 2224/32145 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06562 (2013.01);
Abstract

A stacked die structure for a semiconductor device generally includes a primary level with a first die formed in a wafer, and a second level with a second die coupled to the first die. A third level includes a third die coupled to the second die. The levels have conductive first, second, and third interconnects, respectively, extending from active sides of the dies and may be bonded prior to stacking the dies. The dies may be stacked in an offset or rotated position relative to each other such that the interconnects extend beyond each of the other dies to contact a redistribution layer that forms electrical connections with external components. In some configurations, a fourth level having a fourth die and a conductive fourth interconnect is coupled to the third die and positioned laterally offset from the third die such that the third interconnect extends beyond the fourth die.


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