The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Nov. 30, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Tae Hwan Kim, Hwaseong-si, KR;

Jae Choon Kim, Incheon, KR;

Kyung Suk Oh, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 35/32 (2006.01); F25B 21/02 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 23/38 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 23/38 (2013.01); H01L 23/3121 (2013.01); H01L 23/3738 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 24/16 (2013.01); H01L 25/16 (2013.01); H01L 24/73 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/73204 (2013.01);
Abstract

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip bumps between the first package substrate and the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, a molding member which covers the plurality of second semiconductor chips, on the first semiconductor chip, and a thermoelectric cooling layer attached onto a surface of the first semiconductor chip. The thermoelectric cooling layer includes a cooling material layer extending along the surface of the first semiconductor chip, a first electrode pattern which surrounds the plurality of first chip bumps from a planar viewpoint, in the cooling material layer, and a second electrode pattern which surrounds the first electrode pattern from the planar viewpoint, in the cooling material layer.


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