The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Apr. 28, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aman Sewani, Sunnyvale, CA (US);

Nazar Haider, Fremont, CA (US);

Ankush Varma, Portland, OR (US);

Lan Vu, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); G06F 1/08 (2006.01); G06F 1/32 (2019.01); G06F 1/3296 (2019.01);
U.S. Cl.
CPC ...
G06F 11/3062 (2013.01); G06F 1/08 (2013.01); G06F 1/3296 (2013.01); G06F 11/3024 (2013.01);
Abstract

A scheme is provided for a processor to measure or estimate the dynamic capacitance (Cdyn) associated with an executing application and take a proportional throttling action. Proportional throttling has significantly less impact on performance and hence presents an opportunity to get back the lost bins and proportionally clip power if it exceeds a specification threshold. The ability to infer a magnitude of power excursion of a power virus event (and hence, the real Cdyn) above a set power threshold limit enables the processor to proportionally adjust the processor operating frequency to bring it back under the limit. With this scheme, the processor distinguishes a small power excursion versus a large one and reacts proportionally, yielding better performance.


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