The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2024

Filed:

Aug. 09, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyunmog Park, Seoul, KR;

Daehyun Kim, Suwon-si, KR;

Jinmin Kim, Seoul, KR;

Hei Seung Kim, Suwon-si, KR;

Hyunsik Park, Seoul, KR;

Sangkil Lee, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); G11C 14/00 (2006.01); G11C 16/04 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 25/00 (2006.01); H10B 41/00 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); G11C 13/00 (2006.01); H10B 41/41 (2023.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); G11C 14/0018 (2013.01); G11C 16/04 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); G11C 13/0004 (2013.01); H10B 41/41 (2023.02);
Abstract

Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.


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