The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2024
Filed:
Aug. 16, 2023
Intel Corporation, Santa Clara, CA (US);
Joydeep Ray, Folsom, CA (US);
Aravindh Anantaraman, Folsom, CA (US);
Abhishek R. Appu, El Dorado Hills, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);
Valentin Andrei, San Jose, CA (US);
Subramaniam Maiyuran, Gold River, CA (US);
Nicolas Galoppo Von Borries, Portland, OR (US);
Varghese George, Folsom, CA (US);
Mike Macpherson, Portland, OR (US);
Ben Ashbaugh, Folsom, CA (US);
Murali Ramadoss, Folsom, CA (US);
Vikranth Vemulapalli, Folsom, CA (US);
William Sadler, Folsom, CA (US);
Jonathan Pearce, Portland, OR (US);
Sungye Kim, Folsom, CA (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.