The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Jan. 18, 2023
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Yingdong Guo, Hefei, CN;

Jing Xu, Hefei, CN;

Wei Jiang, Hefei, CN;

Xue Shan, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/02 (2006.01); H05K 1/02 (2006.01); H04B 1/04 (2006.01);
U.S. Cl.
CPC ...
H03K 21/02 (2013.01); H05K 1/0296 (2013.01); H04B 1/04 (2013.01);
Abstract

A layout structure and a method for fabricating the same. A frequency divider pattern layer includes a first frequency divider region, a second frequency divider region, a third frequency divider region and a fourth frequency divider region arranged centrosymmetrically. A conductor pattern layer includes a first sub-conductor pattern layer and a second sub-conductor pattern layer stacked. The first sub-conductor pattern layer is configured to communicate the first frequency divider region with the second frequency divider region, and communicate the third frequency divider region with the fourth frequency divider region. The second sub-conductor pattern layer is configured to communicate the first frequency divider region with the fourth frequency divider region, and communicate the second frequency divider region with the third frequency divider region. The embodiments reduce a channel transmission difference between different frequency dividers in a frequency divider structure.


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