The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Dec. 23, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Daniel Gruber, St. Andrae, AT;

L Mark Elzinga, Shingle Springs, CA (US);

Martin Clara, Santa Clara, CA (US);

Giacomo Cascio, Villach, AT;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/24 (2006.01); H04B 1/16 (2006.01); H04W 88/08 (2009.01);
U.S. Cl.
CPC ...
H03H 11/24 (2013.01); H04B 1/1607 (2013.01); H04W 88/08 (2013.01);
Abstract

An attenuator circuit is provided. The attenuator circuit includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair. Further, the attenuator circuit includes a first plurality of resistive elements coupled in series between the first input node and a first output node for outputting a first output signal. The attenuator circuit additionally includes a second plurality of resistive elements coupled in series between the second input node and a second output node for outputting a second output signal. In addition, the attenuator circuit includes a shunt path coupled to a first intermediate node and a second intermediate node. The first intermedia node is arranged between two resistive elements of the first plurality of resistive elements. The second intermedia node is arranged between two resistive elements of the second plurality of resistive elements. The shunt path comprises a switch circuit configured to selectively couple the first intermediate node and the second intermediate node based on one or more control signals.


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