The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2024
Filed:
Dec. 23, 2020
Intel Corporation, Santa Clara, CA (US);
Sally Amin, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A stacked voltage regulator (VR) that pre-charges inductor switching node to mitigate EOS. The stacked VR comprises at least three n-type devices (low-side) and three p-type devices (high-side) coupled in series. The three p-type stacked devices are part of a high-side of the VR. Node Vx coupling one of the n-type devices and one of the p-type devices is coupled to an inductor, which is also coupled to a load capacitor. During the inductor charging phase, in the low-to-high transition, a small p-type device is added to pre-charge the inductor switching node (V) from '0' to “VDD−Vth” through the low-side by connecting a generated mid-rail “Vdd” to the internal node of the n-type stack for a short period (e.g., about 50 ps). A controlled conductance modulation (CCM) scheme on the high-side top switch during the inductor charging phase is used to mitigate the ringing without controlling the gate drive strength.