The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Dec. 02, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Errol Todd Ryan, Albuquerque, NM (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); G11C 5/06 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); G11C 5/06 (2013.01); H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/76802 (2013.01); H01L 21/76841 (2013.01); H01L 21/76877 (2013.01); H01L 24/14 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02);
Abstract

A semiconductor fabrication method, a semiconductor device and a semiconductor module. The method comprises: providing a stack on a substrate, the stack including a plurality of device layers comprising electrically conductive layers; patterning the stack using an etch to form trenches extending therethrough and pillars between the trenches; providing a carbon-containing liner on sidewalls of the trenches; wet cleaning and drying the stack after providing the carbon-containing liner; filling spaces between the pillars with one or more materials; and electrically coupling contact lines to the electrically conductive layers to form the semiconductor device. The carbon-containing liner may include a carbon-doped liner, such as a carbon-doped oxide liner provided by way of atomic layer deposition of an oxide at temperatures between about 100 degrees Celsius to about 300 degree Celsius using carbon as a precursor.


Find Patent Forward Citations

Ryan, Errol. (2024). Device, method and system to prevent pattern collapse in a semiconductor structure (U.S. Patent No. 12113012). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12113012

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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