The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Jun. 02, 2022
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Chun-Cheng Liao, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/7684 (2013.01); H01L 21/76879 (2013.01); H01L 24/03 (2013.01); H01L 24/80 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53266 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 25/0652 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/0362 (2013.01); H01L 2224/05017 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/06139 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80203 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01);
Abstract

The present application discloses a method for fabricating a semiconductor device. The method includes providing a first chip comprising a first substrate, a first redistribution layer positioned above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad positioned above the first substrate and distant from the first lower bonding pad. The method also includes providing a second chip comprising a dense region and a loose region adjacent to the dense region; a plurality of upper pads positioned on the first lower bonding pad and the second lower bonding pad; and a plurality of second redistribution layers positioned on the plurality of upper pads. The method further performs bonding the second chip onto the first chip in a face-to-face manner, wherein the plurality of upper pads contact the first lower bonding pad and the second lower bonding pad.


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