The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Mar. 20, 2023
Applicants:

Silicon Storage Technology, Inc., San Jose, CA (US);

The Regents of the University of California, Oakland, CA (US);

Inventors:

Farnood Merrikh Bayat, Goleta, CA (US);

Xinjie Guo, Goleta, CA (US);

Dmitri Strukov, Goleta, CA (US);

Nhan Do, Saratoga, CA (US);

Hieu Van Tran, San Jose, CA (US);

Vipin Tiwari, Dublin, CA (US);

Mark Reiten, Alamo, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/54 (2006.01); G06F 3/06 (2006.01); G06N 3/04 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2023.01); G11C 16/08 (2006.01); G11C 16/12 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 29/38 (2006.01);
U.S. Cl.
CPC ...
G11C 11/54 (2013.01); G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0688 (2013.01); G06N 3/04 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/16 (2013.01); G11C 16/3436 (2013.01); G11C 29/38 (2013.01);
Abstract

Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods. In one example, a circuit for converting a current in a neural network into an output voltage comprises a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and a switch for selectively coupling the word line terminal to the bit line terminal; wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.


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