The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Jun. 27, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Christopher J. Hughes, Santa Clara, CA (US);

Alexander F. Heinecke, San Jose, CA (US);

Robert Valentine, Kiryat Tivon, IL;

Menachem Adelman, Haifa, IL;

Evangelos Georganas, San Mateo, CA (US);

Mark J. Charney, Lexington, MA (US);

Nikita A. Shustrov, Novosibirsk, RU;

Sara Baghsorkhi, Los Gatos, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30043 (2013.01); G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 9/30098 (2013.01); G06F 9/30145 (2013.01);
Abstract

Embodiments for gathering and scattering matrix data by row are disclosed. In an embodiment, a processor includes a storage matrix, a decoder, and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode and a first operand field to specify a set of irregularly spaced memory locations. The execution circuitry is to, in response to the decoded instruction, calculate a set of addresses corresponding to the set of irregularly spaced memory locations and transfer a set of rows of data between the storage and the set of irregularly spaced memory locations.


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