The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Sep. 26, 2021
Applicant:

Ceremorphic, Inc., San Jose, CA (US);

Inventors:

Lizy Kurian John, Austin, TX (US);

Heonchul Park, Pleasanton, CA (US);

Venkat Mattela, San Jose, CA (US);

Assignee:

Ceremorphic, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/52 (2013.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 21/52 (2013.01); G06F 9/3001 (2013.01); G06F 9/30076 (2013.01); G06F 2221/033 (2013.01);
Abstract

A secure processor with fault detection has a core thread which executes with a redundant branch processor thread. In one configuration, the core thread is operative on a fully functional core processor configured to execute a complete instruction set, and the redundant branch processor thread contains only initialization instructions and flow control instructions such as branch instructions and is operative on a redundant branch processor which is configured to execute a subset of the complete instruction set, specifically a branch control variable initialization and a branch instruction, thereby greatly simplifying the redundant branch processor architecture. Fault conditions are detected by comparing either a history of branch taken/not taken and branch targets, or a comparison of program counter activity for the core thread and redundant branch processor thread.


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