The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2024
Filed:
Aug. 11, 2023
Applicant:
Rambus Inc., San Jose, CA (US);
Inventors:
Frederick A. Ware, Los Altos Hills, CA (US);
Ely Tsern, Los Altos, CA (US);
Assignee:
Rambus Inc., San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 11/16 (2006.01); G11C 7/10 (2006.01); G11C 29/00 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/52 (2006.01); H03M 13/15 (2006.01); G06F 11/20 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1044 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G06F 11/1666 (2013.01); G11C 7/10 (2013.01); G11C 29/42 (2013.01); G11C 29/4401 (2013.01); G11C 29/52 (2013.01); G11C 29/70 (2013.01); H03M 13/1575 (2013.01); G06F 11/20 (2013.01); G11C 2029/4402 (2013.01); G11C 29/765 (2013.01);
Abstract
A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.