The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2024

Filed:

Mar. 02, 2022
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Teruo Okina, Yokkaichi, JP;

Shinsuke Yada, Yokkaichi, JP;

Ryo Yoshimoto, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); G11C 16/04 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); G11C 16/0483 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H01L 2224/06181 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80001 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1451 (2013.01);
Abstract

A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located on a distal surface of the alternating stack, a dielectric spacer layer located on a distal surface of the semiconductor material layer, memory opening fill structures vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, and a source layer located on a distal surface of the dielectric spacer layer and contacting pillar portions of the vertical semiconductor channels that are embedded within the dielectric spacer layer.


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