The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2024

Filed:

Sep. 22, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Younseok Choi, Seoul, KR;

Byungsun Park, Suwon-si, KR;

Youngil Lee, Wonju-si, KR;

Jaechul Lee, Hwaseong-si, KR;

Jiwoon Im, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor device includes a lower memory stack disposed on a substrate and including lower gate electrodes and a lower staircase structure, an upper memory stack including upper gate electrodes and an upper staircase structure, a lower interlayer insulating layer doped with an impurity and covering the lower staircase structure, the lower interlayer insulating layer having a doping concentration gradually increasing toward the lower staircase structure, an upper interlayer insulating layer doped with an impurity and covering the upper staircase structure and the lower interlayer insulating layer, the upper interlayer insulating layer having a doping concentration gradually increasing toward the upper staircase structure and the lower interlayer insulating layer, lower contact plugs and upper contact plugs contacting the lower gate electrodes and the upper gate electrodes, respectively.


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