The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2024

Filed:

Dec. 23, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aiswarya M. Pious, Bangalore, IN;

Raji James, Bangalore, IN;

Phani K. Alaparthi, Benguluru, IN;

George Vergis, Portland, OR (US);

Bill Nale, Livermore, CA (US);

Konika Ganguly, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G06F 1/3225 (2019.01); G06F 1/3228 (2019.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 5/148 (2013.01); G06F 1/3225 (2013.01); G06F 1/3228 (2013.01); G06F 1/3243 (2013.01); G06F 1/3296 (2013.01); G11C 5/141 (2013.01); G11C 5/147 (2013.01); G11C 11/4074 (2013.01); G11C 2207/2227 (2013.01);
Abstract

Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.


Find Patent Forward Citations

Loading…