The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2024

Filed:

Dec. 14, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Saurabh Sethi, Mohali, IN;

Madhukar Reddy N, Hyderabad, IN;

Vasantha Kumar Bandur Puttappa, Bangalore, IN;

Amulya Srinivasan Margasahayam, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/406 (2006.01); G11C 11/4093 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40618 (2013.01); G11C 11/40615 (2013.01); G11C 11/4093 (2013.01);
Abstract

Aspects of the present disclosure are directed to techniques and procedures for reducing memory (e.g., DRAM) access latency (e.g., read latency, write latency) due to memory refreshes. In some aspects, a memory refresh scheduling algorithm can take into account of memory access batching (e.g., read batch, write batch). In some aspects, a refresh scheduling algorithm can schedule more or prioritize refreshes to occur during a write batch to reduce memory read access latency because fewer refreshes are scheduled during memory read access. The techniques can be adapted to reduce write latency.


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