The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2024

Filed:

Sep. 30, 2020
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Carmine Cappetta, Battipaglia, IT;

Thomas Boesch, Rovio, CH;

Giuseppe Desoli, San Fermo Della Battaglia, IT;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/04 (2023.01); G06F 9/38 (2018.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06N 3/063 (2023.01); G06T 7/11 (2017.01);
U.S. Cl.
CPC ...
G06N 3/04 (2013.01); G06F 9/3806 (2013.01); G06F 13/1657 (2013.01); G06F 13/1673 (2013.01); G06F 13/4022 (2013.01); G06N 3/063 (2013.01); G06T 7/11 (2017.01); G06T 2207/20084 (2013.01);
Abstract

A convolutional accelerator framework (CAF) has a plurality of processing circuits including one or more convolution accelerators, a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, and a stream switch coupled to the plurality of processing circuits. The reconfigurable hardware buffer has a memory and control circuitry. A number of the variable number of input data channels is associated with an execution epoch. The stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch. The control circuitry of the reconfigurable hardware buffer configures the memory to store data of the variable number of input data channels, the configuring including allocating a portion of the memory to each of the variable number of input data channels.


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