The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Sep. 22, 2021
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Chien-Te Feng, Frisco, TX (US);

Wen Yin, San Diego, CA (US);

Jay Scott Salmon, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/36 (2006.01); H01L 23/522 (2006.01); H01L 23/60 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/56 (2013.01); H01L 23/31 (2013.01); H01L 23/36 (2013.01); H01L 23/60 (2013.01); H01L 24/20 (2013.01);
Abstract

A device comprising a package and a board. The package includes a substrate comprising a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a back side metal layer coupled to a back side of the integrated device, a first solder interconnect coupled to the back side metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate. The board is coupled to the package through the plurality of solder interconnects. The first solder interconnect is coupled to the board.


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