The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Mar. 08, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Tung-Huang Chen, Hsinchu, TW;

Yen-Yu Chen, Taichung, TW;

Po-An Chen, Taichung, TW;

Soon-Kang Huang, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 21/321 (2006.01); H01L 23/535 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82385 (2013.01); H01L 21/28088 (2013.01); H01L 21/28114 (2013.01); H01L 21/28123 (2013.01); H01L 21/3212 (2013.01); H01L 21/823842 (2013.01); H01L 23/535 (2013.01); H01L 27/092 (2013.01); H01L 29/42376 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method of manufacturing a semiconductor device having metal gates and the semiconductor device are disclosed. The method comprises providing a first sacrificial gate associated with a first conductive type transistor and a second sacrificial gate associated with a second conductive type transistor disposed over the substrate, wherein the first conductive type and the second conductive type are complementary; replacing the first sacrificial gate with a first metal gate structure; forming a patterned dielectric layer and/or a patterned photoresist layer to cover the first metal gate structure; and replacing the second sacrificial gate with a second metal gate structure. The method can improve gate height uniformity during twice metal gate chemical mechanical polish processes.


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