The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Oct. 11, 2021
Applicant:

Nuvoton Technology Corporation, Taiwan, CN;

Inventors:

Bal S. Sandhu, Fremont, CA (US);

Paul Vande Voorde, San Mateo, CA (US);

Chang-Xian Wu, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 27/00 (2006.01); H10B 41/30 (2023.01);
U.S. Cl.
CPC ...
G11C 16/045 (2013.01); G11C 11/5635 (2013.01); G11C 27/005 (2013.01); H01L 23/5223 (2013.01); H10B 41/30 (2023.02);
Abstract

A floating-node memory device includes a metal-oxide-semiconductor (MOS) transistor including a first polysilicon gate, a source region, and a drain region in a first well region, a tunneling device including a second polysilicon gate in a second well region, and a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer. The floating-node device includes a floating-node comprising the first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor coupled together, a control node at the bottom plate of the MIM capacitor, an erase node in the second well region, a source node at the source region of the MOS transistor, and a drain node at the drain region of the MOS transistor.


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