Flash memory device configured to be bonded to external semiconductor chip and computing device including flash memory device coupled to neural processor chip

Abstract

Flash memory device includes: first pads to be bonded to external semiconductor chip, to receive at least one of command, address and control signals; second pads to be bonded to external semiconductor chip; memory cell array including memory cells; a row decoder block connected to memory cell array through word lines, to select one of word lines based on address provided to row decoder block; a buffer block to store command and address and provide address to row decoder block; a page buffer block connected to memory cell array through bit lines, connected to second pads through data lines without passing through buffer block, and configured to exchange data signals with external semiconductor chip through data lines and second pads; and a control logic block configured to receive command from buffer block, to receive control signals from external semiconductor chip, and to control row decoder block and page buffer block.