The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Jun. 09, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Guifen Yang, Hefei, CN;

Sungsoo Chi, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01); G11C 11/4091 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); H10B 12/50 (2023.02); G11C 7/06 (2013.01); G11C 2207/002 (2013.01);
Abstract

A readout circuit architecture and a sense amplification circuit are provided. The readout circuit architecture includes: a readout amplification unit including a first P-type transistor and a second P-type transistor; and a first offset compensation unit including a first offset compensation transistor and a second offset compensation transistor. The first P-type transistor is arranged in a first area and the second P-type transistor is arranged in a second area. When the first area and the second area are arranged at interval in a first direction, the first offset compensation transistor and the second offset compensation transistor are arranged in a third area located between the first area and the second area. When the first area and the second area are arranged adjacently in the first direction, the first offset compensation transistor is arranged in a fourth area and the second offset compensation transistor is arranged in a fifth area.


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