The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Jul. 13, 2023
Applicant:

Pseudolithic, Inc., Santa Barbara, CA (US);

Inventors:

James Buckwalter, Santa Barbara, CA (US);

Michael Hodge, Huntersville, NC (US);

Justin Kim, San Jose, CA (US);

Daniel Green, McLean, VA (US);

Florian Herrault, Agoura Hills, CA (US);

Assignee:

PseudolithIC, Inc., Santa Barbara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G01R 31/3187 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3187 (2013.01); G01R 31/31704 (2013.01); G01R 31/318511 (2013.01); G01R 31/318513 (2013.01);
Abstract

An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.


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