Stacked neural device structure and manufacturing method thereof

Abstract

This invention provides a stacked neuron device structure and a manufacturing method thereof. The device comprises: a substrate with peripheral circuits in the substrate; a barrier layer; a neuron transistor array, comprising a plurality of neuron transistors arranged in an array, wherein the transistor comprises a semiconductor channel, a modulation stack, and a gate array; the two ends of the semiconductor channel are respectively connected to peripheral circuits, and the peripheral circuit is used to control the gating or closing of the corresponding neuron transistor. The first dielectric layer, the weighting floating gate layer and the second dielectric layer are stacked in this order. The gate array is located on the modulation stack and is used to modulate the potential of the weighting floating gate to realize the weighting of the weight floating gate. The invention realizes a structure and manufacturing method of a junctionless neuron device arranged in an array on a plane and vertically stacked in the longitudinal direction. The on and off of each neuron transistor is controlled by the peripheral circuit in the substrate, which greatly improves the packing density of the neuron devices.