The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

May. 29, 2019
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Kazuya Konishi, Tokyo, JP;

Yoichiro Tarui, Tokyo, JP;

Hiroki Niwa, Tokyo, JP;

Hiroaki Okabe, Tokyo, JP;

Hiroshi Watanabe, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7395 (2013.01); H01L 29/1608 (2013.01); H01L 29/66333 (2013.01);
Abstract

Provided is a technology that suppresses the removal of collector layers in the planarization process while suppressing the snapback phenomenon. A semiconductor device related to a technology disclosed in the present specification includes a drain layer of first conductivity type in a part of a lower surface a drift layer, a plurality of collector layers of second conductivity type in parts of the lower surface of the drift layer, and a dummy layer of the first conductivity type interposed between the plurality of collector layers in parts of the lower surface of the drift layer, in which a width of the dummy layerin a first direction, which is the direction in which the dummy layer is interposed between the plurality of collector layers, is narrower than a width of the drain layer in the first direction.


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