The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2024
Filed:
Aug. 18, 2023
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Arun Sitaram Athreya, Folsom, CA (US);
Shankar Natarajan, Folsom, CA (US);
Sriram Natarajan, Folsom, CA (US);
Yihua Zhang, Folsom, CA (US);
Suresh Nagarajan, Folsom, CA (US);
Assignee:
Intel NDTM US LLC, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3427 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01);
Abstract
In one example, reads in a NAND memory device are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.