The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2024
Filed:
Jul. 17, 2023
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Jonathan M. Eastep, Portland, OR (US);
Richard J. Greco, West Linn, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3203 (2019.01); G06F 1/3234 (2019.01); G06F 1/324 (2019.01); G06F 1/329 (2019.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 1/3265 (2013.01); G06F 1/329 (2013.01); G06F 9/4893 (2013.01); G06F 9/5094 (2013.01); G06N 20/00 (2019.01);
Abstract
Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.