The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2024
Filed:
Sep. 26, 2020
Intel Corporation, Santa Clara, CA (US);
Vivek Garg, Folsom, CA (US);
Ankush Varma, Portland, OR (US);
Krishnakanth Sistla, Portland, OR (US);
Nikhil Gupta, Portland, OR (US);
Nikethan Shivanand Baligar, Hillsboro, OR (US);
Stephen Wang, Hillsboro, OR (US);
Nilanjan Palit, Northborough, MA (US);
Timothy Yee-Kwong Kam, Portland, OR (US);
Adwait Purandare, Hillsboro, OR (US);
Ujjwal Gupta, Hillsboro, OR (US);
Stanley Chen, Portland, OR (US);
Dorit Shapira, Portland, OR (US);
Shruthi Venugopal, Hillsboro, OR (US);
Suresh Chemudupati, Austin, TX (US);
Rupal Parikh, Hillsboro, OR (US);
Eric Dehaemer, Shrewsbury, MA (US);
Pavithra Sampath, Hudson, MA (US);
Phani Kumar Kandula, Hillsboro, OR (US);
Yogesh Bansal, Beaverton, OR (US);
Dean Mulla, Saratoga, CA (US);
Michael Tulanowski, Fort Collins, CO (US);
Stephen Paul Haake, Sunnyvale, CA (US);
Andrew Herdrich, Hillsboro, OR (US);
Ripan Das, Beaverton, OR (US);
Nazar Syed Haider, Fremont, CA (US);
Aman Sewani, Sunnyvale, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.