The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2024
Filed:
May. 18, 2023
Kepler Computing Inc., San Francisco, CA (US);
Sasikanth Manipatruni, Portland, OR (US);
Yuan-Sheng Fang, Oakland, CA (US);
Robert Menezes, Portland, OR (US);
Rajeev Kumar Dokania, Beaverton, OR (US);
Gaurav Thareja, Santa Clara, CA (US);
Ramamoorthy Ramesh, Moraga, CA (US);
Amrita Mathuriya, Portland, OR (US);
Kepler Computing Inc., San Francisco, CA (US);
Abstract
An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.