The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Mar. 17, 2023
Applicant:

Ememory Technology Inc., Hsinchu, TW;

Inventors:

Yu-Hsuan Cheng, Hsinchu County, TW;

Cheng-Heng Chung, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H03K 3/037 (2006.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H03K 3/037 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02);
Abstract

A voltage level shifter includes an input transistor, a control circuit, a reset circuit, and a keeper circuit. The input transistor is configured to receive an input voltage and a first reference voltage. The control circuit is configured to generate a pulse voltage according to the input voltage and one of a node voltage, an output voltage, and an inversion input voltage. The reset circuit is configured to receive the first reference voltage and a second reference voltage and controlled by the pulse voltage. The reset circuit is coupled to the input transistor at a first node where the node voltage is generated. The keeper circuit is coupled to the first node and configured to generate the output voltage according to the node voltage, the first reference voltage, the second reference voltage, and the output voltage.


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