The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Sep. 13, 2021
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventors:

Norio Yasuhara, Ishikawa, JP;

Yoko Iwakaji, Tokyo, JP;

Yusuke Kawaguchi, Ishikawa, JP;

Daiki Yoshikawa, Ishikawa, JP;

Kenichi Matsushita, Ishikawa, JP;

Shoko Hanagata, Ishikawa, JP;

Tomoko Matsudai, Tokyo, JP;

Hiroko Itokazu, Kanagawa, JP;

Keiko Kawamura, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H03K 17/567 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7397 (2013.01); H01L 29/407 (2013.01); H01L 29/41708 (2013.01); H01L 29/42304 (2013.01); H03K 17/567 (2013.01); H01L 29/42372 (2013.01);
Abstract

This semiconductor device includes: a semiconductor layer having a first face and a second face, the semiconductor layer including a first trench and a second trench in a first face side; a first gate electrode in the first trench; a first conductive layer in the first trench and between the first gate electrode and the second face, the first conductive layer being electrically separated from the first gate electrode; a second gate electrode in the second trench; a second conductive layer in the second trench and between the second gate electrode and the second face; a first electrode on a the first face side; a second electrode on a side of the second face; a first gate electrode pad being electrically connected to the first gate electrode; and a second gate electrode pad being electrically connected to the second gate electrode.


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