The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Jun. 18, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Hernan A. Castro, Shingle Springs, CA (US);

Stephen W. Russell, Boise, ID (US);

Stephen H. Tang, Fremont, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/768 (2006.01); H01L 27/04 (2006.01); H05K 1/11 (2006.01); H05K 3/00 (2006.01); H05K 3/22 (2006.01); H10B 99/00 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/76816 (2013.01); H01L 27/04 (2013.01); H05K 1/116 (2013.01); H05K 3/0094 (2013.01); H05K 3/225 (2013.01); H10B 99/00 (2023.02); H10B 63/84 (2023.02);
Abstract

Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.


Find Patent Forward Citations

Loading…