The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Dec. 26, 2021
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Yuta Tamai, Matsumoto, JP;

Hiromichi Gohara, Matsumoto, JP;

Takafumi Yamada, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 25/105 (2013.01);
Abstract

A semiconductor apparatus includes first and second semiconductor chips, and a circuit board. The circuit board is a laminated board sequentially including an insulating plate, a circuit layer, and a metal layer. The circuit layer includes a first mounting portion on which the first semiconductor chip is installed, a second mounting portion on which the second semiconductor chip is installed, and a first and second upper surface slit provided between the first and second mounting portion and extending in a first direction. The metal layer includes a first lower surface slit extending in the first direction. In a plan view, the first mounting portion, the first upper surface slit, the second upper surface slit, and the second mounting portion are provided side by side in the second direction. The first lower surface slit is located within a range defined by the first and second upper surface slit.


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