The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Apr. 22, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chung-Ting Ko, Kaohsiung, TW;

Wen-Ju Chen, New Taipei, TW;

Tai-Chun Huang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/0259 (2013.01); H01L 21/30604 (2013.01); H01L 21/3081 (2013.01); H01L 21/823807 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method for forming a semiconductor structure is provided. The method includes forming first and second fin structures, wherein each of the first and the second fin structurez include first semiconductor layers and second semiconductor layers alternatingly stacked, and forming a first mask structure to cover the second fin structure. The first mask structure includes a first dielectric layer and a second dielectric layer over the first mask structure, and the first dielectric layer and the second dielectric layer are made of different materials. The method also includes forming a first source/drain feature in the first fin structure, removing the first mask structure, forming a second source/drain feature in the second fin structure, removing the first semiconductor layers of the first fin structure and the second fin structure, thereby forming first nanostructures and second nanostructures, and forming a gate stack around the first and second nanostructures.


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